1. Field of the Invention
The present invention relates to a method for manufacturing a solid-state imaging device by use of wafer level chip size packaging technique, and a solid-state imaging device manufactured by such manufacturing method.
2. Description of the Related Art
Digital cameras, equipped with a solid-state imaging device and a semiconductor memory device, are widely spread among consumers. In addition, small electric apparatus, such as a mobile phone and a personal digital assistance (PDA), has the solid-state imaging device and the memory device to enable digital photography. A conventional solid-state imaging device is manufactured by the following steps. First, a solid-state imaging element chip, such as a charge coupled device (CCD) formed on a wafer, is die-bonded on a package formed from a ceramic, for instance. Then, after the terminals of the solid-state imaging element chip and the terminals of the package are electrically connected by bonding wires, a glass lid formed from a transparent glass is fixed to the package to seal the solid-state imaging element chip.
Small solid-state imaging device is preferable in terms of miniaturizing the digital camera and the small electric apparatus. As for an example to reduce the size of the solid-state imaging device, a wafer level chip size packaging technique (hereinafter referred to as “wafer level CSP”) can package the solid-state imaging device without the packaging material. For instance, Japan Patent Laid-Open Publication (JP-A) No. 2002-231921 describes the solid-state imaging device, manufactured by the wafer level CSP technique, in which a spacer is bonded to the peripheral area of the upper surface of the solid-state imaging element chip. The cover glass is provided on the spacer to seal the solid-state imaging element chip. The solid-state imaging element chip has connection terminals on the upper, bottom or lateral surface.
In manufacturing the solid-state imaging device by the wafer level CSP technique, plural spacers are formed on the glass substrate as the cover glass. Then, after adhesives are applied to the edge surface of the spacers, the glass substrate is adhered to a wafer on which plural solid-state imaging element chips are formed. The wafer with the glass substrate is subject to dicing process to manufacture the solid-state imaging device.
It is necessary to provide a space between the solid-state imaging element and the spacer for the purpose of preventing flare that is caused by entering incident light, reflected on the inner surface of the spacer, into the solid-state imaging element. Moreover, since the spacer is pressed onto the solid-state imaging device to generate a stress during the bonding process, the spacer and the solid-state imaging device are distorted. Thus, the space between the solid-state imaging element and the spacer is necessary for preventing such distortion to the solid-state imaging device. Furthermore, because the solid-state imaging element generates much heat when the solid-state imaging device is operated at a high clock rate or takes an image for a long exposure time, the difference in thermal expansion rate between the solid-state imaging element chip and the spacer causes stress. The space between the solid-state imaging element and the spacer is necessary to prevent such stress from affecting the solid-state imaging element.
In bonding the spacer to the wafer, if the adhesives are flowed on the solid-state imaging element chip, the solid-state imaging device does not work properly because of noise interference caused by the flowed adhesive. Moreover, if the gap between the spacer and the wafer is not tightly sealed, the solid-state imaging device is damaged by cooling water during the dicing process. Thus, in order to increase productivity, the spacer must be tightly bonded to the wafer.
For the purpose of proper bonding, the adhesives applied on the spacer must be thin and uniform in thickness over the applied area. Although a small amount of adhesive with high viscosity is dropped on the spacer by potting method according to the above publication, putting the adhesives on the spacer having the width less than 200 μm is technically difficult. Even if the spacer has the width more than 200 μm, dropping the adhesives on all bonded surfaces of the plural spacers takes too much time for the adhering process.
In addition the above publication describes a method to apply the adhesive to the spacer by printing, but printing the adhesive is hardly realized because it is difficult to control the thickness and the position of the adhesive to be printed on the spacer. Moreover, silicon spacer tends to repel the adhesive, so it is also difficult to control the thickness and flatness of the adhesives to be put on the spacer.
In order to bond the spacer properly to the wafer, the width of the frame-shaped spacer is necessary to be considered. If the width of the spacer is too large, an improper bonding will happen because of air remaining inside the adhesive. Moreover, large width spacer will make it difficult to decrease the size of the solid-state imaging device. Thus, the manufacture cost will increase because of the small number of solid-state imaging devices per wafer. On the other hand, if the width of the spacer is too narrow, the solid-state imaging device will be physically weak.
For the purpose of preventing the adhesive from flowing into the solid-state imaging element, it is effective to lengthen the distance between the solid-state imaging element and the spacer. Making the distance longer, however, will increase the manufacture cost because of difficulty in miniaturizing the solid-state imaging device.